1. Field of the Invention
This invention relates to the fabrication of semiconductor devices. More particularly, it relates to the fabrication of interconnection metallurgy systems atop the semiconductor devices.
2. Description of the Prior Art
Advances in modern semiconductor device technology have allowed increasing numbers of devices and circuits to be fabricated within a single semiconductor chip. This has required increasing microminiaturization of semiconductor elements as well as the interconnection metallurgy system connecting the elements within the chip into circuits. Such miniaturization results in decreased costs and improved performance in integrated circuits but is constantly crowding the fabrication technology, particularly the photolithographic and etching techniques of the interconnection metallurgy.
In integrated circuit logic design, for example, thousands of impurity regions are conventionally fabricated in a silicon chip, approximately 125-200 mils squared. Such regions form transistors, diodes, resistors and the like which are then connected together by wiring patterns atop the chip to form various circuits and for connection to input-output terminals.
This interconnection metallurgy system atop the chip is extremely complex and usually employs two or three separate levels of complex conductive patterns, each separated by one or more layers of dielectric material. Ordinarily, the first level conductive pattern on the chip surface interconnects the transistors, resistors, diodes, etc. into circuits and also provides for circuit-to-circuit connections. The latter function is usually provided by parallel lines connected to the individual circuits. The second level conductive pattern conventionally completes the circuit-to-circuit connections and makes contact to I/O terminals which are connectable to a support such a module, substrate or card. The second level usually consists of parallel lines that are transverse to the aforementioned parallel lines of the underlying first level conductive pattern.
Alternatively, a third level may be required for power and I/O connections.
The area occupied within the semiconductor chip by the active and passive semiconductor devices utilized in the various circuits actually occupies a small amount of the total area of the chip. The support area for the metallurgy is the primary factor in determining its size.
At the present state of technology, the lower limits of the width of an interconnection metallurgy stripe are thought to be imposed primarily by photolithographic technology. The line widths are in the order of 0.15 mils with a separation on the order of 0.15 mils for long lines. However, a more severe restriction exists using conventional techniques to form multi-level conductive patterns. At present it is necessary to etch the dielectric layers to form feedthrough patterns from one level to another. Most commonly, after the etching process, the second metallurgy layer is deposited over the dielectric layer and into the via holes to contact the first metallurgy layer.
However, overetching of one dielectric layer due to, say, mask misalignment may result in the etching of a lower dielectric layer. To compensate for such a contingency, it is common to provide increased areas of metallurgy, termed pads, at via hole sites. These pads do effectively prevent overetching but also substantially increase the chip area required for interconnection metallurgy.
One solution to this problem is found in U.S. Pat. No. 3,844,831 issued in the names of E. E. Cass et al., and assigned to the same assignee as the present invention. The Cass et al., technique involves the use of dielectric layers of dissimilar etching characteristics, whereby an etchant which attacks one type of dielectric does not substantially affect the other.
Although the Cass et al., invention has been successful, dielectric etching still is recognized as causing shorts, pinholes and contamination, no matter how controlled the process.
It is therefore desirable to be able to form interconnections between levels of metallurgy without the necessity of etching the dielectric layer.